ISSN 1991-2927
 

ACP № 2 (56) 2019

Hardware Implementation of the Optimal Ldpc Decoder

Georgii Mikhailovich Tamrazian, Ulyanovsk State Technical University, ost-Graduate Student at the Department of Telecommunications of Ulyanovsk State Technical University; graduated from Ulyanovsk State Technical University; an author of articles and patents in the field of redundant code soft decoding. [e-mail: This email address is being protected from spambots. You need JavaScript enabled to view it. ]G. Tamrazian,

Anatolii Afanasievich Gladkikh, Ulyanovsk State Technical University, Candidate of Engineering; graduated from S.M. Budyonny Military Communications Academy; finished his post-graduate studies at the same academy; Professor at the Department of Telecommunications at Ulyanovsk State Technical University; an author of a monograph, textbooks, articles, and patents in the field of noiseless coding and information security. [e-mail: This email address is being protected from spambots. You need JavaScript enabled to view it. ]A. Gladkikh,

Dmitrii Vladimirovich Ganin, Nizhny Novgorod State University of Engineering and Economics, Candidate of Economics, Associate Professor; graduated from Nizhny Novgorod State Agricultural Academy; Head of the Department of Infocommunication Technologies and Telecommunications at Nizhny Novgorod State University of Engineering and Economics; an author of articles in the field of infocommunications. [e-mail: This email address is being protected from spambots. You need JavaScript enabled to view it. ]D. Ganin

Hardware Implementation of the Optimal Ldpc Decoder 000_14.pdf

Low Density Parity Check (LDPC) codes become more useful in modern infocommunication systems because of their error-correcting capability. At the present time, LDPC codes have reached Shannon’s limit. Moreover, the application of such codes unlike the turbo codes don’t have any license limitations. These factors have become the cause of growing interest to LDPC codes. Despite an easy way of the codec implementation, soft decoding of LDPC codes is a complex computational process. This article deals in more detail with the main problems concerning the hardware implementation of LDPC decoder and the ways of their solving. It also demonstrates the simulation results of different ways to decoder implementation and the comparison of these ways. Furthermore, the article presents the method of LDPC codes list decoding that reduces materially computational load on decoder and speeds up its work operation. The use of various procedures and mechanisms described in the article will help to generate the optimal LDPC code decoder designed for a certain task.

Ldpc-код, ldpc code, soft decoder, fpga, cluster, tanner graph, list decoding.

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